High frequency semiconductor devices are employed to form high frequency semiconductor circuits for communication and/or logic operations. The high frequency semiconductor devices may be a metal-oxide-semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT), a passive device such as a capacitor or an inductor, or any other semiconductor device that requires operation at a high frequency, which is typically greater than 1 GHz.
To characterize the high frequency semiconductor devices, high frequency measurements are required. High frequency measurement on a semiconductor device requires a pad set to allow access of a probe, which may be a vector network analyzer (VNA), to the semiconductor device due to microscopic dimensions of the semiconductor device and macroscopic dimensions of the components of the probe. Thus, the probe tests the semiconductor device by transmitting signals to, and receiving signals from, the semiconductor device through the pad set. An inherent consequence of the use of the pad set is that a device test structure (DTS), or the structure tested by the probe, is not an isolated semiconductor device, which is herein referred to as an “intrinsic device” or “device under test” (DUT), but a combination of the intrinsic device and the pad set. In other words, any test data from the DUT invariably involves effects of parasitic components of the pad set that are external to the DUT. The DUT is “embedded” in the device test structure in the sense that any measurement on the intrinsic device must be performed through the entirety of the device test structure, which contains the DUT and the pad set.
Test result obtained from the device test structure includes parasitic effects of the pad set. To extract device characteristics of the DUT, the device characteristics of the inherent device need to be “de-embedded” from the measured data of the DTS since the device characteristics of the inherent device are embedded within the measured data by virtue of the embedding of the inherent device within the DTS. In general, the pad set introduces significant parasitic effects at high measurement frequencies.
Referring to FIG. 1, a DTS containing a DUT and a pad set is shown. If each of the DTS and the DUT is treated as a 2-port network respectively, the pad set that generates the parasitic effect on the intrinsic device is a 4-port network. The electrical effect of the pad set is herein referred to as the “pad set parasitics.” The first port 101 of the 4-port network comprises a port of the DTS. The second port 102 of the 4-port network comprises another port of the DTS. The third port 103 of the 4-port network comprises a connection point to the DUT. The fourth port 104 of the 4-port network comprises another connection point to the DUT.
Unfortunately, the 4-port network and the DUT are unknown. All measurement data is based on measurement on the DTS as a whole. To facilitate de-embedding of the measurement data, calibration standards are used to estimate and subtract the effects of the pad set parasitics of the 4-port network. Exemplary calibration standards include an “open dummy” or an “open network,” a “short dummy” or a “short network,” a “thru dummy” or a “thru network,” the structures and netlist representations of which are described in Table 1.
TABLE 1Physical structures and netlist representations of commondummies in prior art de-embedding methodsType ofcalibrationstandardPhysical structureNetlist representationThru dummyDUT removed from DTS4-port network with the thirdand the third port 103port 103 and the fourth portand the fourth port 104104 directly connectedare connectedOpen dummyDUT removed from DTS4-port network with the thirdport 103 and the fourth port104 openShort dummyDUT removed from DTS4-port network with the thirdand the third port 103port 103 and the fourth portand the fourth port 104104 shortedare shorted
Traditionally, de-embedding is performed in two steps. Commonly used prior art de-embedding method is open-short (O-S) de-embedding, which requires two additional calibration standards of an open dummy and a short dummy. The open-short de-embedding simplifies the 4-port network by assuming that dominant parasitics are either near the probe pad or near the DUT, and are not distributed.
Referring to FIG. 2, an equivalent circuit for the 4-port network according to the O-S de-embedding method is shown. The equivalent circuit according to the O-S de-embedding comprises a first open parasitics component 210A, a second open parasitics component 210B, and a third open parasitics component 210C. The first open parasitics component 210A is connected directly between the two nodes of the first port 201 of the 4-port network, which is a first port of the DTS. The second open parasitics component 210B is connected directly between the two nodes of the second port 202 of the 4-port network, which is a second port of the DTS. The third open parasitics component 210C is connected between a signal node (marked with a “+” sign, as opposed to a ground node that is marked with a “−” sign) of the first port 201 of the 4-port network and a signal node of the second port of the 4-port network.
The equivalent circuit according to the O-S de-embedding further comprises a first short parasitics component 220A, a second short parasitics component 220B, and a third short parasitics component 220C. The first short parasitics component 220A is connected directly between the signal node of the first port 201 of the 4-port network and a signal node of the third node 203 of the 4-port network, which is a first port of the DUT. The second short parasitics component 220B is connected directly between the signal node of the second port 202 of the 4-port network and a signal node of the fourth node 204 of the 4-port network, which is a second port of the DUT. The third short parasitics component 220C is connected directly between the combined ground nodes (between which no parasitic components are assumed to be present in the O-S de-embedding method) of the third and fourth ports (203, 204) of the 4-port network and the combined ground nodes (between which no parasitic components are assumed to be present in the O-S de-embedding method) of the first and second ports (201, 202) of the 4-port network.
Referring to FIG. 3, a prior art open-short (O-S) de-embedding method is shown in a flow chart. Referring to step 310, scattering parameter (S-parameter) data is measured on the embedded device test structure containing the device under test (DUT) and the pad set. Scattering parameters are parameters that describe electrical behavior of a linear electrical network subjected to steady state stimuli by small electrical signals. In general, various electrical properties of the linear electrical network such as signal gain, return loss, voltage standing wave ratio, refection coefficient, and amplifier stability may be described with S-parameters. The idea behind the S-parameters is that the response of the linear electrical network may be considered as scattering of an input signal within the linear electrical network. Of particular concern for estimating the pad set parasitics with the prior art O-S de-embedding method are Y-parameters that represent admittance of the 4-port network and Z-parameters that represent impedance of the 4-port network.
Referring to step 320, the measured S-parameters are converted to Y-parameters. Methods of converting S-parameters to Y-parameters in a 2-port network are known in the art. Specifically, U.S. Pat. No. 7,075,312 to Fabry et al., U.S. Pat. Nos. 7,026,829 and 7,071,707 to Tiemeijer, U.S. Pat. No. 6,961,669 to Brunsman, U.S. Pat. Nos. 6,832,170 and 6,665,628 to Martens, U.S. Pat. No. 6,815,964 to Di Gregorio et al., and U.S. Pat. No. 6,211,541 to Carroll et al. are incorporated herein. It is noted that the S-parameters, Y-parameters, and Z-parameters of a 2-port network are given by 2×2 matrices.
Referring to step 330, calculations for subtracting open parasitics, i.e., the collective parasitics of the first open parasitics component 210A, the second open parasitics component 210B, and the third open parasitics component 210C, are performed at a predetermined frequency. The first operation calculates an open de-embedded DTS admittance YDTS—OP—DEEM, which is the admittance of the set of the DUT and the short parasitics, i.e., the collective parasitics of the first short parasitics component 220A, the second short parasitics component 220B, and the third short parasitics component 220C. The open de-embedded DTS admittance, YDTS—OP—DEEM is given by:YDTS—OP—DEEM=YDTS−YOPEN,  (Equation 1)wherein YDTS is the calculated admittance of the DTS that contains the DUT, the open parasitics, and the short parasitics, and wherein YOPEN is the calculated admittance of an open dummy that is supposed to contain only the open parasitics. The calculated admittance of the DTS YDTS and the calculated admittance of the open dummy, YOPEN are based on the S-parameters of the DTS and the open dummy that are measured at the predetermined frequency.
The second operation calculated a short de-embedded DTS admittance YSHORT—OP—DEEM, which is the admittance of the short parasitics that contains the collective parasitics of the first short parasitics component 220A, the second short parasitics component 220B, and the third short parasitics component 220C. The short de-embedded DTS admittance, YSHORT—OP—DEEM is given by:YSHORT—OP—DEEM=YSHORT−YOPEN,  (Equation 2)wherein YSHORT is the calculated admittance of a short dummy that is supposed to contain the open parasitics and the short parasitics. The calculated admittance of the short dummy, YSHORT is based on the S-parameters of the short dummy that are measured at the predetermined frequency.
Referring to step 340, a DUT Z-parameter, which is the Z-parameter of the DUT, is calculated. The DUT Z-parameter ZDUT is given by:ZDUT=Y−1DTS—OP—DEEM−Y−1SHORT—OP—DEEM,  (Equation 3)wherein Y−1DTS—OP—DEEM is the inverse matrix of the open de-embedded DTS admittance YDTS—OP—DEEM and Y−1SHORT—OP—DEEM is the inverse matrix of the short de-embedded DTS admittance, YSHORT—OP—DEEM.
Referring to step 350, the DUT Z-parameter ZDUT is converted back to an S parameter. It is noted that the manipulation of measured S-parameters is done for the preset frequency and that there is no fitting or any variable parameter in the prior art O-S de-embedding method. Thus, execution of one round of the calculation process provides DUT Z-parameter ZDUT at one frequency. To generate a frequency dependent profile for DUT Z-parameter ZDUT, the calculation process is repeated at multiple frequencies one frequency at a time.
While the open-short (O-S) de-embedding method provides a simple scheme for estimating the pad set parametrics, the assumption on dominant parametrics and nature of distribution of the pad set parametrics is not true in many cases, and introduces significant errors especially at high frequency, e.g., in GHz frequency ranges and above. This problem becomes more profound in noise de-embedding particularly in bulk complementary metal-oxide-semiconductor (CMOS) technology, which employs a bulk substrate that induces a large signal loss.
Some other de-embedding techniques have been proposed in the prior art to enhance accuracy of estimation of the 4-port network representing the pad set parasitics. For example, a “three step” de-embedding method employing 3 calibration standards and assuming a 9 element network for the 4-port network is known in the art. U.S. Patent Application Publication No. 2006/0114004 A1 to Tiemeijer that discloses the three step de-embedding method is herein incorporated by reference. A 4-port de-embedding method employing 4 to 6 calibration standards and assuming a 15 element network for the 4-port network is also known in the art. Q. Liang, et al., “A Simple Four-Port Parasitic Deembedding Methodology for High-Frequency Scattering Parameter and Noise Characterization of SiGe HBTs,” IEEE Trans. Microwave Theory and Techniques, v. 51, n. 11, pp. 2165-2174 (2003) that discloses the complete de-embedding method is herein incorporated by reference. However, use of additional calibration standards to enhance accuracy of the de-embedding increases device characterization cost both by increasing a total test structure area on a semiconductor chip and by increasing the complexity of testing and data analysis. While benefits of use of increased number of calibration standards are known, the prior art methods also incur significant increase in cost, oftentimes rendering the characterization methods uneconomical.
In view of the above, there exists a need for an improved system and methods for representing the 4-port network of the pad set with an enhanced accuracy in the estimation of the of the pad set parasitics.
Further, there exists a need for an improved system and methods for de-embedding a device test structure in which a device under test (DUT) is embedded to extract device characteristics of the DUT with an enhanced accuracy.